🚀 We’re Hiring: Physical Design Engineer (ASIC)
๐ Vancouver, BC, Canada (Onsite)
๐ Contract: 12โ18 months
Weโre hiring a Physical Design Engineer for a leading global networking and semiconductor company. Youโll join an ASIC Physical Design team and own full-chip physical implementation from RTL to GDSII on advanced technology nodes.
What you’ll do
๐น Own physical design implementation of multi-hierarchy designs: physical-aware synthesis, DFT, floorplanning, placement, CTS and routing
๐น Drive Static Timing Analysis (STA) and timing signoff closure
๐น Perform IR Drop/EM analysis and physical verification (DRC/LVS) through signoff
๐น Optimize designs for Power, Performance and Area (PPA)
๐น Work with Front-End/RTL teams to understand the design architecture and resolve implementation issues
๐น Build and improve automation scripts and physical design flows
What we’re looking for
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BS/MS in Electrical Engineering, Computer Engineering or Computer Science
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5+ years of hands-on ASIC physical design and implementation experience
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Strong skills in floorplanning, PnR, CTS, timing closure and hierarchical design
โ
Hands-on experience with industry-standard EDA tools (Synopsys, Cadence; Calibre/ICV for PV)
โ
Experience with EM/IR and physical verification signoff
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Scripting in Tcl, Python or Perl
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Eligible to work in Canada
Nice to have
โ Formal verification (LEC) experience
โ Experience with advanced nodes (5nm/3nm) and complex SoC integration
📩 Interested? DM me or comment “Interested” and I’ll reach out. Referrals are welcome!
Equal Employment Opportunity: We are an equal opportunity employer. All qualified applicants will be considered for employment without regard to race, colour, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, Indigenous status, veteran status, or any other characteristic protected by applicable law. We are committed to an inclusive and accessible hiring process. Accommodations are available on request at any stage.
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